Pipeline Trace Decoder

Use pipeline to convert a detailed simulation log into pipeline.bin, or extract one tile's trace as JSON. For interactive inspection, launch Portrait from a tutorial's GOAL=debugx output directory and select a tile.

Command-Line Usage

Creating a Binary Trace

pipeline arch=sdr log=bench-sim.log trace=pipeline.bin

Option	Description
arch=<arch>	Architecture of the log, e.g. sdr. Always name it: the default is not sdr.
log=<file>	Input simulator log file
trace=<file>	Output binary trace file

Extracting a Tile as JSON

pipeline trace=pipeline.bin tile=T<col>.<row>

This loads the specified tile's data from the binary file and outputs JSON to stdout.

Reading a trace

Look for long stalls, missing receives, and repeated instructions. Compare the cycle where data arrives with the cycle where it is consumed. A trace can only show events recorded in its input log; use files from the same run.

Pipeline Stages

SDR traces show these 11 pipeline stages:

Index	Name	Full Name	Meaning
0	pf	Pre-Fetch	Instruction address generation
1	fm	Fetch Memory	Instruction memory access
2	f	Fetch	Instruction fetch / decode
3	c	Check	Dependency/hazard checking
4	d	Decode	Full instruction decode
5	r	Read	Register/operand read
6	e	Execute	ALU/FPU execution
7	m	Memory	Memory access stage
8	x	eXtend	Extended execution / completion
9	w	Write-back	Result write-back to register file
10	wm	Write Memory	Memory write-back

• Schrödinger (11-stage pipeline): pf → fm → f → c → d → r → e → m → x → w → wm

JSON output

Tile JSON includes archname, a pipeline array of cycle records, and an insn array of instructions. Stage entries identify the instruction and whether it stalled or advanced. Instruction sequence entries include cycles, operand addresses, and values. Use Portrait to navigate these together with the source listing.